以并发性为视角探究VeriIogHDL代码的优化策略

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中图分类号：TN47；TP312 文献标识码：A 文章编号：2096-4706（2025）24-0083-04

Abstract：Inthe teachingof proceduralassignments intheVeriloghardwaredescriptionlanguage，studentsoftenconfuse non-blockingassignments withblockingasignments，leadingtosignificant deviations betweenthe designed circuitsand the expectedresults.Thisproblemisparticularlyprominentincomplex digitalcircuitdesign.Taking typicaldigitalcircuitdesignas examples，thispaperclarifies theessential differencesbetwennon-blocking assignments andblocking assignments inpractical applications bycomparing indetail the impacts of these two assignment methods on RTL circuits.Through the analysis of optimizeddesigns，itisconcluded thatonthepremiseofensuringcorrectlogical functions，theadoptionofthenon-blocking assignment method can better guarantee the accuracy and work effciency of students'circuit designs.

Keywords：Verilog; blocking assignment; non-blocking assignment; RTL

0 引言

在Verilog中，过程赋值可以采用两种写法，即阻塞性赋值和非阻塞性赋值[1-2]，这两种赋值方式的正确使用一直是初学者的困扰，尤其对于有过单片机系统开发经验的初学者来说，习惯了代码的顺序执行逻辑，更容易将Verilog的两种赋值方式混淆[3-4]。（剩余4919字）